Integrated circuit technologies continue to evolve. Computing and communications designs are incorporating more functionality, higher processing and transmission speeds, smaller feature sizes, more memory, etc., into smaller and more robust architectures.
Semiconductor memories in particular are evolving at a rapid pace. Memory devices have reduced power requirements, increased capacities, increased operating frequencies, reduced latencies, etc., all while ramping with the exponential density increases according to Moore's Law.
The increased frequencies of memory devices have necessitated greater bandwidth between the memory devices and memory controllers. Prior memory systems, such as the initial double data rate (DDR) DRAMs, often had multi-drop bus architectures that were terminated with a resistor on the motherboard the bus resided on. With subsequent generations of memory such as DDR2 and GDDR3, the termination resistor was moved on die with the memory to improve the signal integrity for these high frequency systems.
Transistors often display process variations even on the same integrated circuit. In MOS transistors, for example, process variations may occur in impurity concentration densities, oxide thicknesses, diffusion depths, or generally by variations during diffusion of impurities or during deposition. Process variations cause transistor parameters to vary. Other variations often exist due to voltage or temperature drifts during operation. In combination, process, voltage and temperature (PVT) variations affect integrated circuit performance.
DDR2 memory systems would calibrate on die termination resistors during power up and compensate for process variations. DDR2 memory systems also provided off-chip driver (OCD) calibrations to reduce mismatch between pull-up and pull-down output driver characteristics, further improving timing margins in the memory. Signaling was not sufficiently fast in DDR2 systems to require a compensation for voltage and temperature variations. DDR2 systems would either not calibrate at all to account for process variations or would calibrate once during initialization.
In GDDR3 graphics devices, calibration is done during auto-refresh operations to compensate for voltage and temperature variations. In these GDDR3 calibrations, a memory controller initiates a refresh cycle in the DRAM.
In a refresh cycle, charge loss in memory cells is compensated for by periodically rewriting the cell contents. Refresh operations consist of a read of memory cell contents followed by rewriting the cell contents. This refresh operation is why DRAMs are called dynamic RAMs.
Refresh operations take a relatively long time in DRAM cycles, currently in the area of 200 nanoseconds to 400 nanoseconds. In GDDR3 memory systems, the DRAM could run a hidden calibration in the background during refresh. However, calibrations run during refresh are not very accurate due to significant signal noise on the DRAM device from the refresh operation while the device opens several rows and writes them back to refresh cells in the memory.
What is needed is an improved method and apparatus to more effectively calibrate termination and drive circuitry to account for process voltage and temperature variations.